1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and particularly, to a semiconductor memory circuit equipped with two inverters in antiparallel connection.
2. Description of the Background Art
FIG. 25 is a circuit diagram showing a construction of a memory cell 80 of a prior art static random access memory (hereinafter referred to as SRAM). In FIG. 25, memory cell 80 includes: P-channel MOS transistors 81 and 82; and N-channel MOS transistors 83 to 86. P-channel MOS transistors 81 and 82 are connected, respectively, between a line of power supply potential VDD and a storage node N81, and between a line of power supply potential VDD and a storage node N82, and the gates thereof are connected to respective storage nodes N82 and N81. N-channel MOS transistors 83 and 84 are connected, respectively, between a line of ground potential GND and a storage node N81, and between a line of ground potential GND and a storage node N82, and the gates thereof are connected to respective storage nodes N82 and N81. N-channel MOS transistor 85 is connected between a bit line BL and storage node N81, and MOS transistor 86 is connected between a bit line /BL and storage node N82, and the gates thereof are both connected to a word line WL. MOS transistors 81 and 83 constitute an inverter giving an inverted signal of a signal of storage node N82 to storage node N81. MOS transistors 82 and 84 constitutes an inverter giving an inverted signal of a signal of storage node N81 to storage node N82. The two inverters are antiparallel-connected between storage nodes N81 and N82 to constitute a latch circuit.
When word line WL is driven to H level at select level, N-channel MOS transistors 85 and 86 become conductive. When one bit line (for example, BL) of bit lines BL and /BL is driven to H level, and in addition, the other bit line (/BL in this case) is driven to L level according to a write data signal, not only do MOS transistors 81 and 84 become conductive, but MOS transistors 82 and 83 also become non-conductive to thereby latch levels of storage nodes N81 and N82. When word line WL is driven to L level at non-select level, N-channel MOS transistors 85 and 86 become non-conductive to store a data signal into memory cell 80.
In read operation, after bit lines BL and /BL are precharged to H level, word line WL is driven to H level at select level. By doing so, a current flows out from bit line (/BL in this case) onto the line of ground potential GND through N-channel MOS transistors 86 and 84 to lower a potential of bit line /BL. By comparison between potentials on bit lines BL and /BL, storage data of memory cell 80 can be read out.
In such a memory cell 80, a so-called soft error has been easy to occur in company with recent progress to high level of integration and to low level of voltage of power supply. Herein, the term soft error is a phenomenon that xcex1-particle radiation emitted from a trace of radioactive material contained in a package strikes a memory cell to invert storage data. This is considered because a soft error is easy to occur since with a higher level of integration, capacities of storage nodes N81 and N82 are smaller and power supply voltage is lowered.
It is accordingly a main object of the present invention to provide a semiconductor memory circuit, in which storage data is hard to be inverted even when the memory circuit is irradiated with xcex1-particle radiation.
A semiconductor memory circuit according to the present invention includes: two inverters connected between first and second storage nodes, an input node of each inverter being connected to an output node of the other inverter, wherein the inverters each include: plural first transistors with a first conductivity type, connected in series between a line of a first power supply potential and the output node, and whose input electrodes are all connected to the input node; and a second transistor with a second conductivity type, connected in series between a line of a second power supply potential and the output node, and whose input electrode is connected to the input node. Therefore, since an inverter includes the plural first transistors, a capacity of a storage node is larger compared with a prior art case where an inverter includes one first transistor, making storage data hard to be inverted. Furthermore, unless one xcex1-particle passes through the plural first transistors, storage data is not inverted; therefore, the storage data is harder to be inverted compared with a prior case where storage data was inverted by one xcex1-particle passing through one first transistor.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.